In modern microprocessors, the concept of virtual memory is used in conjunction with the physical memory. Virtual memory allows a smaller amount of physical memory (which is important due to cost) to be used with large and/or multiple applications. This is possible due to the fact that only a relatively small portion of any particular application is required to be in physical memory at any one time. Therefore, in computer systems running several applications simultaneously, it is possible to place only the data and code that is needed for the currently running application in physical memory while unused data and code is either left in virtual memory or stored on a hard disk drive.
A paging based memory management uses the concept of pages, each of which typically comprise 4K (thousands of bytes) of memory address. The virtual memory causes the application to believe there is, for example, 4 G (gigabytes) of memory available (for a 32 bit addressing scheme), whereas in reality there is typically anywhere from less than 1 M (megabyte) on up of physical memory (RAM). Thus it is necessary to be able to "swap" pages from physical memory to another location (ie., a disk/secondary storage).
In order to allow swapping in paging based memory management (for example, the "INTEL" Corporation 386 and 486 microprocessors, hereinafter "i386/i486"), it is typical to provide a paging system which serves to map and locate each individual page. Mapping is done by creating and maintaining page tables which list the location of each page in a page table entry (PTE). Thus, when an application requires a specific page, that page may be located by scanning through a page table. The PTE contains the address of the page as well as an accessed/not accessed flag which indicates a most recent usage.
In order to attempt to maximize the efficiency of the swapping into and out of physical memory, operating systems are provided with an ager. The purpose of an ager is to swap the least recently used pages out of physical memory when space is needed. The pages that have not been recently used will first be designated for an "idle" list and then will be swapped out as necessary. Thus, if there are pages not being used, it is more efficient to place them in storage (ie., disk) rather than take up space that may be needed in physical memory. Therefore, the ager and the paging system work in combination to keep track of the location of a page and to keep only the pages that are actually needed in physical memory.
One key determinant of a base operating system's performance is the performance of the paging based memory management, since it can directly impact the rest of the system's performance in the dimensions of working set, response time, and capacity. Thus, it is imperative that the fundamental memory management be carefully designed. In modern microprocessors, support for paging memory management is present but limited.
The efficiency of paging memory management is directly impacted by: (1) the efficiency and effectiveness of the aging, (2) correct identification of the pages which no longer belong in the working set, and (3) length of the aging cycle. By shortening the aging cycle, there will typically be a proportionate decrease in the working set. For over-committed systems, it is imperative that the ager be sufficiently efficient, since the absence of such efficiency will allow the wrong pages to occupy physical memory.
In the paging based memory management architecture of some modern microprocessors such as the "i386/i486", there is a PTE corresponding to each page in memory, as previously described above. The page table entries reside in page tables. Each process has its own separate set of page tables and PTE's. Each time the contents of a page are accessed, an "accessed" flag in the PTE corresponding to that page is set by the base hardware. This flag tells the ager that the page has been accessed (or not accessed) since the last aging service or cycle through that page table. The ager clears the flag after scanning the PTE. Typically the ager must scan all the page tables of all processes in a system to complete one full aging cycle. Periodically the ager scans all the PTEs, checks the status of the bits, and takes the appropriate actions, which could include paging out the pages which were not accessed recently. In the "i386/i486" microprocessors, support for identification of the exact page access pattern including the exact order of access is limited to the "accessed/not accessed" bit in the PTE. In the base hardware, no page level time stamping is available which will tell the paging memory management sub-system the exact order of the page accesses.
It is very important that the time allocated to the ager be utilized carefully: (1) the ager should be efficient at its chosen task of identifying the next set of pages to be paged out, and (2) the ager should be accurate in identifying the pages which need to be paged out. Incorrect decisions in this regard can significantly increase erroneous page-outs, increase the physical memory requirement, and ultimately can reduce the competitiveness of the system. The central processing unit (CPU) time consumed by the ager comes at the expense of the other processes in the system and a complete aging cycle can take several CPU time slices. For efficient utilization of the resources (such as CPU time) consumed by the ager, it is important that the ager judiciously allocate these available resources to different processes.
In addition to the efficiency of the functioning of the ager, it is also important to facilitate a superior selection of the pages designated for an "idle list" which will be paged out next. Current systems utilize an approximation of a least recently used (LRU) method to swap a page out of memory. This method can often lead to incorrect decisions, especially for highly dynamic and over committed systems. As previously described above, once access flags corresponding to two physical pages are set, there is no way for the operating system to determine which page was accessed first. Additionally, once the accessed flags of two PTEs corresponding to two different pages are reset, there is no way for the operating system to determine which one was accessed last. Thus, it is entirely possible that the ager will select an incorrect page (ie., one that was most recently used) to be swapped out.
For example, while scanning PTEs, the ager may detect two PTEs with access flags reset. To the ager, this implies that after these flags were last reset, the pages were not accessed. It can designate both of these pages for the idle list (ie., a list of potential candidates to be paged out) and eventually page out both of them if they are not accessed soon enough. In other words, both pages are treated equally from the perspective of the ager. However, one page can be of a very high usage (eg., a page containing code of a high usage software) which happens to have had no access in the immediate past, while the other page could be a genuinely low usage page. However, the first page has a higher probability of being accessed in the future than the second page. Due to the limitations of the ager, it is possible that when a page needs to be paged out, the first page (ie., the high usage page) could be chosen, since from the limited perspective of the ager, both pages appear the same. Therefore, if the first page needs to be referenced again after being swapped out, a page fault will occur. A page fault typically causes a delay in processing time since the process being run must be halted while the page is located and swapped back into physical memory.
The accessed bit flag is set in a corresponding PTE whenever the page is accessed. The aging process scans the PTEs sequentially to identify the pages which have/have not been accessed and the pages not accessed are eventually designated for the idle list and may be paged out. The scanning process is inherently time consuming. Not all the PTEs in a page table need to be scanned, since only a sub-set of the pages corresponding to these PTEs will be present in physical memory. Typically, a large number of the PTEs may have to be scanned just to find an entry corresponding to a page that is present in physical memory. Essentially a very large number of entries may have to be scanned in order to locate the PTEs corresponding to the pages present in the physical memory.
Thus there is a need for a method and apparatus to more effectively manage memory in a microprocessor. In particular, a method and apparatus which achieves more efficient page aging in a paging based memory management is required.